1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2011-051604, filed Mar. 9, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
Accompanying the nanoscaling of semiconductor devices, in planar-structured transistors using a substrate surface as a channel, it has become difficult to suppress the short-channel effect and to achieve the desired transistor characteristics. The trench-gate type of transistor disclosed in Japanese Patent Application Publications Nos. JPA 2006-339476 and JPA 2007-081095 has come into use to avoid this phenomenon.
In the trench-gate type of transistor noted in Japanese Patent Application Publications Nos. JPA 2006-339476 and JPA 2007-081095, the surface of a trench formed on the inside of the semiconductor substrate is used as a channel. Therefore, because the reduction in the plan-view dimension is compensated for by an increase of the dimension in the depth direction of the trench, it is possible to suppress the short-channel effect.
However, in the trench-gate type of the transistor noted in Japanese Patent Application Publications Nos. JPA 2006-339476 and JPA 2007-081095, the constitution is such that the gate electrode protrudes upward above the surface of the semiconductor substrate, and there is the problem of a deterioration in transistor characteristics caused by offset in the alignment with respect to the trench in the gate electrode process step. In particular when using the gate electrode as a word line, in a DRAM (dynamic random-access memory) constituted to use bit lines arranged so as to intersect with the word lines, the contact plugs connecting the semiconductor substrate to the uppermost layer interconnects must be formed between each of the word lines, which are formed at the minimum process dimension, and the difficulty in forming these contact plugs is a great barrier to the nanoscaling of a DRAM.
Given this, for the purpose of facilitating the forming of the above-noted contact plugs, investigation has been done regarding a buried-gate type of transistor that is completely buried within a trench, without the gate electrode protruding above the semiconductor substrate surface. In a buried-gate transistor, because the word lines are buried within the semiconductor substrate, only the bit lines are the only interconnects of the memory cells that are positioned above the semiconductor substrate surface, thereby having the benefit of reducing the difficulty of processing in the memory cell formation process. A buried-gate transistor is constituted to minimally include a gate electrode (word line) formed to be buried inside a trench formed in the semiconductor substrate, a cap insulating film that protects the upper surface of the gate electrode inside the trench and that has an upper surface that is substantially the same as the surface of the semiconductor substrate, and a bit line is formed above, with an intervening interlayer insulating film that covers the semiconductor substrate surface.